VHDL state machine -
i wrote code in vhdl expected @ rotory switch , feed me position in.
when gets turned read in greycode rotor dial , switch states corresponding greycode state.
the act of changing states tells me way rotor being twisted can indicate either or down state on counter module later in circuit.
if state changes should trigger pulse on mag , triger either 1 or 0 on up_dwn.
it doesn't work when simulate it. occassional blip on mag no up_dwn change.
i suspect it's stuck in thestartstate.
anyone care , tell me i've done wrong?
[ed: using quartus ii version 9 ]
library ieee; use ieee.std_logic_1164.all; entity encoderv2 port( ch_ab : in std_logic_vector (1 downto 0); clk : in std_logic; nreset : in std_logic; up_dwn, mag : out std_logic); end encoderv2; architecture of encoderv2 -- type state_type ( start, s00, s01, s11, s10); signal state: state_type; begin process (clk, nreset) begin if nreset = '0' -- asynch reset 0 state <= start; elsif clk'event , clk = '1' -- triggers on pgt case state when start => if ch_ab ="00" state <= s00; mag <='0'; elsif ch_ab="01" state <= s01; mag <='0'; elsif ch_ab= "11" state <= s11; mag <='0'; elsif ch_ab= "10" state <= s10; mag <='0'; else state <= start; end if; when s00 => -- s10 <- s00 -> s01 if ch_ab= "00" state <= s00; mag <='0'; elsif ch_ab= "10" state <= s10; up_dwn <= '0'; mag <='1'; elsif ch_ab= "01" state <= s01; up_dwn <='1'; mag <='1'; else state <= start; end if; when s01 => -- s00 <- s01 -> s11 if ch_ab= "01" state <= s01; mag <='0'; elsif ch_ab= "00" state <= s00; up_dwn <= '0'; mag <='1'; elsif ch_ab= "11" state <= s11; up_dwn <='1'; mag <='1'; else state <= start; end if; when s11 => -- s01 <- s11 ->s10 if ch_ab= "11" state <= s11; mag <='0'; elsif ch_ab= "01" state <= s01; up_dwn <= '0'; mag <='1'; elsif ch_ab= "10" state <= s10; up_dwn <='1'; mag <='1'; else state <= start; end if; when s10 => -- s11 <- s10 -> s00 if ch_ab= "10" state <= s10; mag <='0'; elsif ch_ab= "11" state <= s11; up_dwn <= '0'; mag <='1'; elsif ch_ab= "00" state <= s00; up_dwn <='1'; mag <='1'; else state <= start; end if; end case; end if; end process; end a;
works fine me ... simulated modelsim
i simuleted 50, 100 , 200 mhz. thing wonder use "if .. nreset = '0' then" .. sure it? cost me 20minutes before saw , changed in stimulus file.
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