Is it possible to write type-generic entities in VHDL? -
so, inherited vhdl code, , first reaction was, "vhdl has structs, why use bit-vectors everywhere?" , realized because there not seem way write this:
entity queue generic ( el : type ); port ( data_in : el; data_out : el; ... ); end entity queue; i wish possible. there remotely approximating it? if have retype entity or component declarations, way avoid retyping architecture definition every (modulo generic width) type?
yes, , implementing queue 1 of classic reasons it!
this has been in vhdl since vhdl-2008. tool support variable of mid-2012. talk slow-moving industry!
- aldec supports completely.
- modelsim has partial support - can't find public link capabilities. if have installed, it's in /technotes/vhdl2008.note
- xilinx (xst/isim) doesn't support it, or vhdl-2002. can't find simple link, these pdfs have sections on vhdl compatibility, talk of vhdl-1993.
- altera's tools have partial support, not type generics
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